Invalidity Analysis — US9349745 (public record)

For attorney review — not a legal opinion, not a validity determination. Every eligible reference in this corpus discloses the general 3D vertical-gate (VG) NAND framework recited in the independent claims (stacks of conductive strips separated by dielectric, orthogonal word lines acting through vertical gate structures, and control circuitry performing nonvolatile operations), and several disclose the peripheral operating biases and charge-storage structures recited in the dependents. However, the target patent's distinguishing limitations — the STAGGERED first/second sets of vertical gate columns, the position-dependent overlie relationship (element 8/9: at one position the first word line overlies a thick dielectric region and no gate column while the adjacent word line overlies a gate column, and vice versa), and the quantified thick-dielectric-region limitation (element 10) — are not disclosed by any single eligible reference, so NO clean §102 anticipation ground exists on this record. The strongest candidate grounds are therefore §103 combinations that pair a VG-NAND base reference with US7851849B2 (which teaches alternating wide/narrow spacings and gate protrusions entering the wide gaps) and/or US8363476B2 (which teaches vertical channel/gate columns formed in cavities between stacked structures and adjacent-line off-biasing). The recurring, dispositive weakness across all grounds is that the staggering geometry itself is absent — US7851849B2 affirmatively teaches an ALIGNED arrangement (all protrusions enter the same wide gaps) and US7420242B2 expressly teaches 'substantial linear alignment,' both of which the patentee will invoke as teaching away or as negating any articulated motivation. These grounds are candidates for the attorney to evaluate, not validity determinations.

Candidate grounds for attorney evaluation, ranked strongest-first — not a validity determination. Confirm every reference date and quotation before relying on a ground.

Ground 1 — §103 obviousness

Strength: moderate
References: A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device, Design innovations to optimize the 3D stackable vertical gate (VG) NAND flash, US8363476B2
Claims: 9, 10, 21, 22
KSR rationale: (G) — MPEP § 2143

Assuming the independent claim is rendered obvious (grounds 1-2), these dependents add only conventional read-biasing of adjacent word lines, which US8363476B2 and the 'Design innovations' read-waveform paper disclose for the same VG NAND context, mapping to claims 9/21 (one adjacent word line off) and 10/22 (two adjacent word lines off on opposite sides).

Motivation to combine: The read-operation dependent claims recite applying a read bias to a selected word line and an off bias to one or two adjacent word lines. US8363476B2 expressly teaches applying an opposite/negative bias to adjacent lines to turn off unselected devices ('applying a second bias voltage to the string selection line of the stacked structure on one sidewall of the channel line not selected and to be turned off ... the first bias voltage is opposite to the second bias voltage') and biasing structures on 'the opposite sidewalls' — i.e., adjacent on both sides. The 'Design innovations' paper teaches 'Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode' for exactly this VG NAND architecture. A PHOSITA operating the VG NAND base device would apply these known adjacent-line off-biasing read schemes (TSM rationale (G)) with a reasonable expectation of successful selection/disturb suppression.

Weakest link: These grounds inherit the independent-claim gap: without a showing that claims 1/11's staggered structure is obvious, the read-bias dependents cannot stand. The mapping of 'off bias to two adjacent word lines on opposite sides' to US8363476B2's SSL biasing is contestable because the reference biases select-gate lines and opposite-sidewall structures, not necessarily two adjacent WORD LINES of the target's staggered layout.

Patentee's likely counterarguments:

• The dependents rise or fall with independent claims 1/11, which are not shown obvious (missing staggered-column geometry).
• US8363476B2's biasing is directed to string-select-line (SSL) decoding of channel columns, not to biasing adjacent WORD LINES controlling staggered gate columns as claimed; the analogy is a mismatch of function (MPEP § 2141.02).
• General read-disturb waveform optimization does not disclose the specific adjacent-and-opposite-sides word-line off-bias arrangement tied to the claimed staggered structure.

Ground 2 — §103 obviousness

Strength: weak
References: A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device, US7851849B2
Claims: 1, 2, 11, 12
KSR rationale: (A) — MPEP § 2143

The VG NAND reference maps to claim-1 elements 1-6 and 11 (stacks of conductive strips separated by dielectric; word lines over and orthogonal acting as vertical gates; control circuitry for nonvolatile operations). US7851849B2 maps to the discrete-gate-in-gap and thick-dielectric-region concept (its 'second spacing' is larger than half pitch and a dielectric-filled 'first spacing' remains where no protrusion enters). Together they would be argued to render obvious a VG NAND in which vertical gate structures occupy some gaps while thicker dielectric occupies others, approaching elements 7-10.

Motivation to combine: The VG TFT NAND reference supplies the base 3D vertical-gate architecture — stacked conductive strips acting as bit lines/channels, vertical gates that control current flow, and X/Y pitch scaling ('The proposed buried-channel VG NAND allows better X, Y pitch scaling'). US7851849B2 supplies the teaching that adjacent stacks can be separated by an alternating narrow ('first spacing') and larger ('second spacing') gap and that the gate electrode's protruding portion enters the wide gap while charge storage is placed there ('spacings between adjacent stacked units having a first spacing and a second spacing larger than the first spacing, the first spacing and the second spacing being alternately provided ... the gate electrode including a protruding portion entering into a gap ... having the second spacing'). A PHOSITA seeking to relax the tight lateral pitch of VG gate structures (a problem both references address) would, per KSR rationale (A), combine the known VG strip/gate architecture with US7851849B2's known variable-spacing technique to obtain a predictable relaxed-pitch gate layout, arguably yielding a vertical-gate-column pitch greater than the word-line pitch (claims 2/12).

Weakest link: Neither reference discloses STAGGERING of a first set of gate columns relative to a second set, nor the element 8/9 position-dependent overlie relationship (one word line over a dielectric region and no column while the adjacent word line is over a column, and vice versa). US7851849B2 affirmatively teaches an ALIGNED arrangement — every gate protrusion enters the same periodic wide 'second spacing' gaps — which is the opposite of the claimed stagger. The quantified element-10 limitation (dielectric-region depth-thickness exceeding the combined thickness of at least two conductive strips) is also not shown.

Patentee's likely counterarguments:

• Missing element: the staggered first/second sets and the element 8/9 overlie geometry are absent from both references, so no §103 case reaches the claim as a whole (MPEP § 2141.02).
• Teaching away / changed principle of operation: US7851849B2's regular 4F-periodic aligned protrusion scheme teaches away from staggering, and reworking it into a staggered layout would change its principle of operation (MPEP § 2143.01).
• No articulated motivation beyond hindsight: the specific benefit of staggering (relaxed column density with intervening thick dielectric regions) is drawn from the target's own disclosure, an impermissible hindsight reconstruction (MPEP § 2145).

Ground 3 — §103 obviousness

Strength: weak
References: US8363476B2, US7851849B2
Claims: 1, 11, 13, 14
KSR rationale: (A) — MPEP § 2143

US8363476B2 provides the structural base (stacked structures/strips, dielectric element between column and stack, columns between stacks acting as gates, control circuitry with read/program biases) and the process steps closely tracking claims 13 and 14. US7851849B2 provides the thick-dielectric-region-between-columns concept. The combination is argued to render obvious the independent claims' column-in-gap architecture and the dependent process claims.

Motivation to combine: US8363476B2 discloses a 3D VG memory in which channel/gate columns are formed in the space between stacked structures, including forming a dielectric element in the gap and forming conductive column material and then removing portions ('forming a dielectric element on the substrate and the stacked structures exposed by the space; forming a conductive material for filling the space; and removing a portion of the conductive material'), directly relevant to the process recitations of claims 13-14 (forming charge storage and gate material in gaps, etching to leave columns separated by holes, and forming dielectric in the holes / forming cavities and forming columns in the cavities). US7851849B2 adds the alternating wide/narrow spacing so that a dielectric-filled region persists between column locations. A PHOSITA fabricating VG columns in gaps (US8363476B2) would, per rationale (A), apply US7851849B2's known variable-spacing patterning to yield a predictable column-and-dielectric-region layout.

Weakest link: US8363476B2's columns are described as channel/gate elements entering every gap in a regular arrangement, not staggered between adjacent word lines; neither reference supplies element 7 (stagger) or the element 8/9 alternating overlie relationship, and element 10's quantified dielectric thickness is unshown. Claim 14 further requires cavities 'centered in the dielectric' — an added structural detail not clearly disclosed.

Patentee's likely counterarguments:

• The dispositive staggered-column and thick-dielectric-region limitations are absent from both references (MPEP § 2131 / § 2141.02).
• US8363476B2's decoding relies on continuous SSL/WL lines and channel columns in every gap; modifying it to a staggered sparse-column layout could render it unsatisfactory for its intended decoding purpose (MPEP § 2143.01).
• Attorney argument alone cannot supply the unexpected benefit of the staggered geometry; no reference articulates a reason to stagger (MPEP § 2145 / § 2143.02).

Ground 4 — §103 obviousness

Strength: weak
References: A highly scalable 8-layer 3D vertical-gate (VG) TFT NAND Flash using junction-free buried channel BE-SONOS device, US8363476B2, US7851849B2
Claims: 5, 6, 7, 8, 17, 18, 19, 20
KSR rationale: (A) — MPEP § 2143

These dependents add conventional SONOS/BE-SONOS charge-storage geometry — curved when surrounding a cavity-formed cylindrical column, flat when on opposite sidewalls of a gap — all disclosed by the cited references in the same VG NAND context, and the 'volume alternates along the length between dielectric fill and a column surrounded/flanked by charge storage' recitation follows directly from a staggered/sparse-column layout.

Motivation to combine: The charge-storage dependents recite curved charge storage layers surrounding the vertical gate columns (5/6/17/18) or flat charge storage layers on opposite sides (7/8/19/20). The VG TFT NAND reference uses BE-SONOS charge-storage dielectric in the VG architecture; US8363476B2 discloses a 'dielectric element disposed between the channel element and the stacked structure' that may be 'an ONO ... or a BE-SONOS composite layers' surrounding the column; US7851849B2 discloses a charge storage layer 'provided between a side face of the semiconductor layers and the protruding portion.' A PHOSITA building the column-in-gap VG device would, per rationale (A), employ these known charge-storage configurations (surrounding/curved for a cavity-formed column, or flat on opposite sidewalls for a slit/gap-formed column) with predictable results, and the claimed alternation of dielectric fill and column-plus-charge-storage along the gap follows from placing columns only at some positions.

Weakest link: The 'alternates along the length between dielectric fill and a column' recitation (claims 6/8/18/20) presupposes the very staggered/sparse-column arrangement (element 7) that no reference discloses; and no reference shows the curved-surrounding charge storage in the specific staggered-column context. The independent-claim gap again controls.

Patentee's likely counterarguments:

• The 'alternating dielectric-fill and column' limitation embeds the unshown staggered geometry, so the dependents fail with the independent claims (MPEP § 2141.02).
• US7851849B2 places charge storage only on the wide 'second spacing' side of an aligned periodic layout, not in the alternating dielectric/column pattern the claims require (teaching away from the staggered configuration).
• Combining three references to reconstruct the specific curved/flat charge-storage-plus-alternation limitation reflects hindsight assembled from the target's own disclosure (MPEP § 2145).

Ground 5 — §103 obviousness

Strength: weak
References: A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts, US7851849B2
Claims: 1, 3, 11, 15
KSR rationale: (E) — MPEP § 2143

This ground attempts to reach the staggered-column limitation (elements 3/7 and 15's gate-column-gap recitation) by analogizing the reference's even/odd 'twist' of bit lines to a staggered offset of the vertical gate columns of adjacent word lines, combined with US7851849B2's variable spacing. It is the only eligible reference that expressly discloses an even/odd opposite-direction offset of any kind.

Motivation to combine: The split-page BL VG NAND reference teaches a manufacturability-driven layout that 'twists the even/odd BL's (and pages) in the opposite direction (split-page BL),' evidencing that alternating/offsetting adjacent structures in opposite directions is a known VG-NAND design lever for manufacturability. A PHOSITA facing the finite, predictable choice between aligned and offset (staggered) adjacent gate-column sets (KSR rationale (E), obvious to try) could apply an analogous even/odd offset to the vertical gate columns of adjacent word lines, with US7851849B2 supplying the wide/narrow spacing that creates room for the offset columns and the intervening dielectric regions.

Weakest link: The reference's 'twist' is of the BIT LINES / pages for split-page decoding, not of vertical GATE COLUMNS controlling adjacent word lines; the analogy is a substantial leap and does not disclose the element 8/9 word-line-over-column/dielectric overlie relationship or element 10's thick dielectric region. This is the ground most vulnerable to a hindsight/non-analogous-application challenge.

Patentee's likely counterarguments:

• The split-page 'twist' concerns bit-line/page layout for decoding, an entirely different structure and problem from staggering gate columns; borrowing it is impermissible hindsight (MPEP § 2145).
• Even granting an offset concept, elements 8, 9, and 10 (the position-dependent overlie geometry and quantified dielectric thickness) remain undisclosed by either reference (MPEP § 2141.02).
• 'Obvious to try' fails because the record identifies no recognized problem prompting a staggered gate-column solution and no reasonable expectation that staggering would predictably work in the VG architecture (MPEP § 2143 rationale (E) / § 2143.02).

Unverified leads (no established date — not usable as grounds)

These references had no establishable date, so they were withheld from the grounds analysis — an undated reference cannot anchor a §102/§103 ground. Undated web results are often post-priority commentary describing the target’s own commercialized feature; treat these strictly as leads to date manually.

• High-density three-dimensional integration of dynamic random-access memory using vertical dual-gate IGZO TFTs - PMC (non-patent literature)
• Multi-Tier 3D SRAM Module Design: Targeting Bit-Line and Word-Line Folding | Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (non-patent literature)

Element-by-element mapping of the strongest prior-art references against the target’s independent claims. A single absent element defeats §102 anticipation for that reference (it may still contribute to a §103 combination). Quoted reference passages are verified verbatim against the fetched reference text; any unverified quote is flagged in the Priority-Date Discipline section. For attorney review.

US6906940B1 — Plane decoding method and device for three dimensional memories vs. claim 1

Verdict: missing element(s) — no §102.

US6906940B1 discloses a three-dimensional multi-layer memory addressed by three mutually orthogonal decoding 'planes' (word plane, drain plane, source plane) intersecting three-terminal memory core cells (e.g., MOSFET/BJT/SET) with state-change elements such as antifuse/fuse/chalcogenide. Only the claims text (no detailed description or figures) was provided. At most the reference partially maps to a general notion of orthogonal word/drain conductors over a 3D array (element 2) and to control/decoding circuitry that applies programming and read voltages and functions as a decoder (element 11). It does NOT disclose the core architecture of target claim 1: there is no plurality of stacks of conductive strips separated by dielectric (element 1), no vertical gate columns acting as gates that control current flow in the strips (elements 3, 5, 6), no first/second adjacent word lines coupled to distinct sets of vertical gate columns (elements 4, 6), and critically none of the staggered-gate-column limitations or the position-dependent overlie/dielectric-region geometry with quantified thickness (elements 7-10). Because multiple limitations — including every distinguishing staggered-gate-column and dielectric-region feature — are absent from this single reference, it would not anticipate claim 1 under §102/MPEP § 2131; the verdict is missing_elements. The reference is a resistance-change/decoding-architecture disclosure fundamentally different from the target's 3D vertical-gate NAND strip-and-gate-column structure, and its unverified detailed description limits any broader reliance.

US6906940B1 — Plane decoding method and device for three dimensional memories vs. claim 11

Verdict: missing element(s) — no §102.

For attorney review — not a legal opinion, not a validity determination. US6906940B1 discloses a plane-decoding scheme for a multi-layer 3D memory built from word planes, drain planes, and source planes accessing three-terminal memory core cells (with fuse/antifuse/chalcogenide state-change elements), and provides decoding/access circuitry that applies voltages and accesses stored values — which maps only loosely onto the claimed 'control circuitry' (element 11, partial) and the orthogonal-plane geometry (element 2, partial). The available text (abstract + claims only) does NOT disclose the core architecture of claim 11: stacks of conductive strips separated by dielectric and gaps (element 1), vertical gate columns between the stacks acting as gates on the strips (elements 3, 5), word lines coupled to first/second sets of vertical gate columns (elements 4, 6), the staggered-column arrangement and its first/second-position overlie relationships (elements 7-9), or the thick dielectric-region limitation exceeding a combined thickness of at least two conductive strips (element 10). Because numerous limitations — most notably the vertical-gate-column and staggered-column elements that are central to the claim — are absent from this single reference, it would NOT anticipate claim 11 under §102 (MPEP § 2131); a §102 rejection cannot be cured by combining the reference with others, and the many gaps here would need to be supplied by other art in a §103 analysis. Note: only the abstract and claims of this reference were provided; the specification/figures were not available, so any broader disclosure is UNVERIFIED.

US7315474B2 — Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays vs. claim 1

Verdict: missing element(s) — no §102.

US7315474B2 is directed to planar (2D) non-volatile SONOS/SONONOS memory cells formed on a semiconductor substrate with source/drain regions, a tunnel dielectric, charge-storage layer, insulating layer, and a gate electrode, arranged in NOR and NAND arrays, together with methods of programming, reading, and self-converging erase. Its available text supports only the operational/control-circuitry limitations (element 11, and, in generic terms, word lines controlled as gates during programming/reading/erase — elements 2 and 4 at most partially) but the core three-dimensional architecture of claim 1 is wholly absent: there is no disclosure of a plurality of stacks of conductive strips separated in a depth direction (element 1), no vertical gate columns between the stacks acting as gates (elements 3, 5, 6), no staggering of first/second sets of vertical gate columns (element 7), no word-line/gate-column overlie relationships at first and second positions (elements 8, 9), and no thick first/second dielectric regions exceeding the combined thickness of at least two conductive strips (element 10). Because multiple independent limitations that define the claimed 3D staggered vertical-gate structure are missing from this single reference, it would not anticipate claim 1 under §102 (MPEP § 2131); at most it could contribute the operating/control-circuitry teachings to a §103 combination, which is outside the scope of this anticipation chart.

US7315474B2 — Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays vs. claim 11

Verdict: missing element(s) — no §102.

US7315474B2 is directed to a planar non-volatile (SONOS/SONONOS/NROM-type) memory cell characterized by a tunnel dielectric structure, charge storage layer, and operating (reset/program/read) methods, with source/drain regions formed in a semiconductor substrate. It discloses generic word lines and nonvolatile memory operations (programming/reading via word-line and substrate voltages), which map only partially to elements 2, 4, and 11. It does NOT disclose the core structural architecture recited in claim 11 — there is no plurality of stacks of conductive strips separated by dielectric in a depth dimension (element 1), no vertical gate columns between stacks (elements 3, 5, 6), no staggered arrangement of two sets of vertical gate columns (element 7), none of the positional stagger relationships between first/second word lines and dielectric regions/gate columns (elements 8, 9), and no thick dielectric-region thickness limitation (element 10). Because multiple limitations are entirely absent from this single reference, it would NOT anticipate claim 11 under §102 (MPEP § 2131); the reference could at most be a secondary teaching (e.g., of BE-SONOS/charge-storage layers or NAND operating biases) in a §103 combination, which would require an articulated motivation to combine and a separate analysis. This is candidate prior-art analysis for attorney review, not a legal opinion or validity determination.

US7420242B2 — Stacked bit line dual word line nonvolatile memory vs. claim 1

Verdict: missing element(s) — no §102.

For attorney review — not a legal opinion, not a validity determination. US7420242B2 discloses a 3D stacked-level anti-fuse crosspoint memory with orthogonally arranged word lines and stacked bit lines interconnected by via plugs through side-wall anti-fuse dielectric. It maps loosely onto the generic architectural framing of claim 1 — stacked conductive lines (bit lines forming a “stack”), orthogonal word lines, word lines coupled to via columns, and addressing/control circuitry — but these are partial, non-corresponding disclosures because the reference is a two-terminal anti-fuse memory, not a vertical-gate transistor NAND. Several core limitations are entirely absent: the via plugs are anti-fuse programming plugs, not “vertical gate columns acting as gates controlling current flow” (element 3); the reference affirmatively teaches the OPPOSITE of staggering, disclosing that the via plugs of the first and second word lines are in “substantial linear alignment” (element 7), so the staggered overlie/dielectric-region relationships of elements 8–9 are unsupported; and there is no disclosure of a dielectric region whose depth-direction thickness exceeds the combined thickness of two conductive strips (element 10). Because at least these limitations are missing from this single reference, it would not anticipate claim 1 under §102 (MPEP § 2131); at most it could be considered as one input to a §103 analysis, which requires a separately articulated motivation to combine. All quoted matter is drawn from text; figure-only relationships (e.g., FIGS. 5–9) not reproduced in the provided text remain UNVERIFIED.

US7420242B2 — Stacked bit line dual word line nonvolatile memory vs. claim 11

Verdict: missing element(s) — no §102.

US7420242B2 discloses an anti-fuse-type stacked nonvolatile memory in which orthogonally-arranged word lines and stacked bit lines are joined through via plugs coated with anti-fuse dielectric, plus addressing circuitry — so it maps loosely onto the generic 'stacks/word lines/orthogonal arrangement/adjacent word-line-pair/addressing circuitry' recitations (elements 1, 2, 4, 6, 11, all partial and using different structures). It does NOT anticipate claim 11 because several core limitations are entirely absent as arranged: the reference's via plugs are anti-fuse interconnect elements, not 'vertical gate columns acting as gates controlling current flow' (elements 3, 5); the reference expressly teaches the plugs in 'substantial linear alignment' rather than the claimed staggered first/second sets (element 7); and there is no disclosure of the staggered-position dielectric-region geometry (elements 8, 9) or the quantified requirement that the dielectric regions exceed a combined thickness of at least two conductive strips (element 10). Because multiple limitations are missing from this single reference, it does not anticipate under §102/MPEP § 2131; at most it could be considered in a §103 combination, which requires a separately articulated motivation to combine. This is a candidate analysis for attorney review, not a validity determination.

US7696559B2 — Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same vs. claim 1

Verdict: missing element(s) — no §102.

This reference discloses a stacked-conductor NAND memory, but its architecture is fundamentally inverted relative to target claim 1 and it therefore does not anticipate. In the reference, the vertically-stacked conductive strips ARE the gate wirings/word lines ('multiple gate wirings are stacked and separated from each other with insulating films'), and the vertical pillars alongside them are pillar-shaped SEMICONDUCTOR channel layers — not gate columns. Claim 1, by contrast, requires stacks of conductive strips (channels) that are controlled by separate vertical GATE columns coupled to word lines that run over and orthogonal to the stacks. Consequently, only element 1 maps to the reference structurally (a stack of conductive strips separated by dielectric), and elements 4 and 11 map partially (word lines and read/write/erase bias operations exist, though the word lines are stacked vertically, not laterally adjacent, and no control circuitry drives the claimed staggered gate-column geometry). The core distinguishing limitations — a plurality of word lines over/orthogonal to the stacks (element 2), vertical gate columns between the stacks acting as gates (elements 3, 5, 6), the staggered first/second sets of gate columns (element 7), the position-dependent overlie relationships (elements 8, 9), and the thick dielectric regions exceeding two conductive-strip thicknesses (element 10) — are all ABSENT from the reference as provided. Because multiple limitations are missing, no §102 anticipation is made out; the reference could at most be considered as one input to a §103 combination, which is outside the scope of this single-reference chart.

US7696559B2 — Semiconductor memory device including pillar-shaped semiconductor layers and a method of fabricating the same vs. claim 11

Verdict: missing element(s) — no §102.

For attorney review — not a legal opinion, not a validity determination. US7696559B2 discloses a fundamentally different 3D NAND architecture from claim 11 and does not anticipate it. The reference's 'gate wiring stack body' with 'multiple gate wirings ... stacked and separated from each other with insulating films' superficially reads on 'stacks of conductive strips separated by dielectric material' (element 1, partially — but note the reference's stacked strips are the WORD-LINE/control-gate wirings themselves, not the current-carrying conductive strips of the target), and the reference discloses control gates and nonvolatile read/write/erase operations relevant to element 11. However, the reference's memory elements are vertical PILLAR-SHAPED SEMICONDUCTOR CHANNELS, not 'vertical gate columns' acting as gates; the reference has no word lines running 'over and orthogonal to' the conductive strips (its bit lines/data lines run orthogonal, and word lines are the horizontally-stacked wirings), and it discloses no staggered vertical gate columns, no first/second dielectric-region overlie relationship, and no dielectric-region thickness limitation. Elements 2–10 are therefore absent. Because multiple core limitations — the vertical gate columns, their staggering, the word-line-over-stacks orientation, and the thick dielectric regions — are missing from this single reference, it would not anticipate claim 11 under §102 (MPEP § 2131); at most it is a candidate component for a §103 analysis, which requires a separate motivation-to-combine showing.

US7851849B2 — Nonvolatile semiconductor storage device and method for manufacturing same vs. claim 1

Verdict: missing element(s) — no §102.

US7851849B2 maps cleanly onto the general 3D NAND framework of claim 1: it discloses stacked units of semiconductor layers separated by insulating layers (element 1, though the reference calls them 'semiconductor layers' rather than 'conductive strips'), orthogonal gate electrodes serving as word lines (element 2, 4), and gate-electrode 'protruding portions' entering gaps between the stacks that act as gates (elements 3, 5, 6, though these are integral protrusions of the gate electrode rather than discrete vertical gate columns). The reference's key architectural feature is an ALTERNATING narrow/wide spacing (first/second spacing) in which every gate electrode's protruding portions enter the SAME wide (second-spacing) gaps — an aligned, not staggered, arrangement. Consequently the central novel limitations of claim 1 are absent: the staggering of the first set of gate columns relative to the second set (element 7), the positional consequences of that stagger whereby one word line overlies a dielectric region while the adjacent word line overlies a gate column and vice versa (elements 8, 9), and the associated depth-direction dielectric-region thickness limitation (element 10). Because these elements are not disclosed and cannot be supplied by combining with the reference itself, this reference does not anticipate claim 1 under §102 (MPEP § 2131); at most it is a candidate building block for a §103 combination the attorney may wish to develop. This is a candidate prior-art analysis for attorney review — not a legal opinion or validity determination.

US7851849B2 — Nonvolatile semiconductor storage device and method for manufacturing same vs. claim 11

Verdict: missing element(s) — no §102.

US7851849B2 discloses the general 3D NAND framework relied on by claim 11 — stacked semiconductor layers separated by insulating layers into juxtaposed stacked units (element 1), a gate electrode aligned orthogonally to and intersecting those stacks (element 2), gate protruding portions entering the gaps to act as gates (elements 3, 5, 6, partially), plural adjacent gate electrodes (element 4), and an associated peripheral circuit (element 11, partially). However, the reference's distinctive teaching is that the wide 'second spacing' gaps are provided at a regular periodic interval (4F) and the gate protruding portions all enter those second-spacing gaps — it does NOT disclose the claim's core staggered-vertical-gate-column architecture. Specifically, elements 7 (first set of columns staggered relative to second set), 8 and 9 (the alternating first/second-position arrangement in which a given word line at one position overlies a dielectric region and no gate column while the adjacent word line overlies a gate column, and vice-versa), and element 10 (the thick dielectric regions whose depth-direction thickness exceeds the combined thickness of at least two conductive strips) are absent from the provided text. Because at least these limitations are missing from this single reference, it would not anticipate claim 11 under §102 (MPEP § 2131); it may, however, be relevant to a §103 analysis if combined with a reference teaching the staggered word-line/gate-column layout.